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Boosting Performance of Face Detection by Using an Efficient Skin Segmentation Algorithm
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High-speed and Pipelined Finite Field Bit-Parallel Multiplier over GF(2 m) for Elliptic Curve Cryptosystems
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Design of a Low- Power and Low- Cost Booth- Shift/ Add Multiplexer- based Multiplier
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Soft-error hardened redundant triggered latch
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Activity aware clock gated storage element design
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Design of a neuromorphic edge detector vision chip with color and intensity change disambiguation
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Fault coverage improvement and test vector generation for combinational circuits using spectral analysis
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A low power D3L 16-bit radix- 4 pipelined SRT divider
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Calibration of analog-to-digital converters based on histogram test methods
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Low-Power State-Retention Dual Edge-Triggered Pulsed Latch
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A Novel 4 2 Compressor for High speed and Low Power Applications
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An electronic marker tag detection smart camera for object localization
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Soft error filtered and hardened latch
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Low-Power Dual-Edge Triggered State Retention Scan Flip-Flop
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A nonlinearity error calibration technique based on an opamp distortion modeling
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A frequency based digital background calibration technique for pipelined ADCs
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A digital pseudo background correction method in pipelined ADCs
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A Class-AB Square-Root Domian Biquad Filter Based on Floating Gate MOS Transistors
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A Second-Order Low Power Current-Mode Continuous-Time Sigma-Delta Modulator
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A Micropower Multi Decade Dynamic Range Current-Mode True RMS-to-DC Converter
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