Low-Power Dual-Edge Triggered State Retention Scan Flip-Flop

Low-Power Dual-Edge Triggered State Retention Scan Flip-Flop
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The 19th International Workshop on Power and Timing Modeling Optimization and Simulation ( PATMOS 2009 )

doi
Article type
Conference
https://people.iut.ac.ir/en/sayedi/content/1658481