Articles

type: Journal
Title DOI Date
Hardware design and implementation of high-efficiency cube-root of complex numbers 10.1016/j.micpro.2023.104847
A structured review of sparse fast Fourier transform algorithms 10.1016/j.dsp.2022.103403
Hardware Implementation of Iterative Method With Adaptive Thresholding for Random Sampling Recovery of Sparse Signals 10.1109/TVLSI.2018.2791351
A Low-Complexity Hardware for Deterministic Compressive Sensing Reconstruction 10.1109/TCSI.2018.2803627
Full-custom hardware implementation of point multiplication on binary Edwards curves for application-specific integrated circuit elliptic curve cryptosystem applications 10.1049/iet-cds.2017.0110
SystemC-AMS Modeling of Photodiode Based on PWL Technique to be used in Energy Harvesting CMOS Image Sensor 10.1016/j.vlsi.2017.08.006
High Resolution Digital Imager Based on Time Multiplexing Algorithm 10.1109/JSEN.2017.2682226
High-performance and high-speed implementation of polynomial basis Itoh Tsujii inversion algorithm over GF(2 m ) 10.1049/iet-ifs.2015.0461
Efficient and low0complexity hardware architecture of Gaussian normal basis multiplication over GF (2 m ) for elliptic curve cryptosystems 10.1049/iet-cds.2015.0337
An efficient and high-speed VLSI implementation of optimal normal basis multiplication over GF(2m) 10.1016/j.vlsi.2016.05.006
type: Conference
Title Date
Using Compressive Sensing Technique in Image Sensing
A Low-Power Cyclic Vernier Time-to-Digital Converter for In Pixel Applications
Low Power SRAM using an Optimal Number of Split Bit Lines and Single-Ended Sensing
Design and Implementation of a Low Power Time-to-Digital Converter for Pixel Application
Hardware Implementation of Moving Object Detection using Adaptive Coefficient in Performing Background Subtraction Algorithm
A Low Area and Low Power Pulse Width Modulation Based Digital Pixel Sensor
A High Throughput Hardware CNN Accelerator Using a Novel Multi-Layer Convolution Processor
A Novel PWM Digital Pixel Sensor with In-pixel Memory Structure
Low Power Approximate Unsigned Divider Design Using Gate Diffusion Input Logic
Reduced Complexity Architecture for Normalization of Histogram of Oriented Gradients