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A High-Speed Low-Power Multitask Digital Vision Chip
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A Face Detector Based on Color and Texture
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Boosting Performance of Face Detection by Using an Efficient Skin Segmentation Algorithm
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Reconfigurable Hardware Implementation of Gigabit UDP/IP Stack Based on Spartan-6 FPGA
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High-speed and Pipelined Finite Field Bit-Parallel Multiplier over GF(2 m) for Elliptic Curve Cryptosystems
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Design of a Low- Power and Low- Cost Booth- Shift/ Add Multiplexer- based Multiplier
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Activity aware clock gated storage element design
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Soft-error hardened redundant triggered latch
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Design of a neuromorphic edge detector vision chip with color and intensity change disambiguation
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Fault coverage improvement and test vector generation for combinational circuits using spectral analysis
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A low power D3L 16-bit radix- 4 pipelined SRT divider
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Calibration of analog-to-digital converters based on histogram test methods
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