Implementation of a low power 16-bit radix-4 pipelined SRT divider using a modified Split-Path Data Driven Dynamic Logic (SPD3L) structure Original Research Article

Implementation of a low power 16-bit radix-4 pipelined SRT divider using a modified Split-Path Data Driven Dynamic Logic (SPD3L) structure Original Research Article
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doi
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Date : 1392-09
Article type
Journal
https://people.iut.ac.ir/en/sayedi/content/1624046